HL Disassemble

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Original documents can be seen at https://cdn.preterhuman.net/texts/computing/hotline_info/HL_DISAS.TXT and https://cdn.preterhuman.net/texts/computing/hotline_info/HL_DISAS.1

HL Disassemble
v1.0
Buddy Ha©kit
13-Jul-1997

Notes:
I am not the author of this.


    23E8: 7C08 02A6              proc28   mfLR    r0                      ; Move From Special Purpose Reg
    23EC: 93E1 FFFC                       stw     r31,-4(SP)              ; Store Word
    23F0: 93C1 FFF8                       stw     r30,-8(SP)
    23F4: 93A1 FFF4                       stw     r29,-12(SP)
    23F8: 9001 0008                       stw     r0,8(SP)
    23FC: 9421 FF70                       stwu    SP,-$90(SP)             ; Store Word with Update
    2400: 7C7D 1B78                       mr      r29,r3                  ; Move Reg
    2404: 7C9E 2378                       mr      r30,r4
    2408: 7CBF 2B78                       mr      r31,r5
    240C: 4800 014D      1002558          bl      proc29                  ; Branch , set LR
    2410: 6000 0000                       nop                             ; No op
    2414: 3800 002A                       li      r0,42                   ; Load Immed
    2418: B01D 0018                       sth     r0,24(r29)              ; Store Halfword
    241C: 387D 001C                       addi    r3,r29,28               ; Add Immed
    2420: 7FC4 F378                       mr      r4,r30                  ; Move Reg
    2424: 88BE 0000                       lbz     r5,0(r30)               ; Load Byte and Zero
    2428: 38A5 0001                       addi    r5,r5,1                 ; Add Immed
    242C: 4803 4A71      1036E9C          bl      proc1171                ; Branch , set LR
    2430: 6000 0000                       nop                             ; No op
    2434: 887E 0000                       lbz     r3,0(r30)               ; Load Byte and Zero
    2438: 3803 0005                       addi    r0,r3,5                 ; Add Immed
    243C: 901D 0220                       stw     r0,$220(r29)            ; Store Word
    2440: 3860 003A                       li      r3,58                   ; Load Immed
    2444: 389E 0001                       addi    r4,r30,1                ; Add Immed
    2448: 88BE 0000                       lbz     r5,0(r30)               ; Load Byte and Zero
    244C: 4803 4655      1036AA0          bl      proc1160                ; Branch , set LR
    2450: 6000 0000                       nop                             ; No op
    2454: 2803 0000                       cmpli   cr0,0,r3,0              ; Compare Logical Immed
    2458: 4182 000C      1002464          bc  IF,cr0_EQ,lbc_1             ; Branch Conditional
    245C: 3800 0000                       li      r0,0                    ; Load Immed
    2460: 4800 0008      1002468          b       lbc_2                   ; Branch
    2464: 3800 157C              lbc_1    li      r0,$157C                ; Load Immed
    2468: B01D 001A              lbc_2    sth     r0,26(r29)              ; Store Halfword
    246C: 281F 0000                       cmpli   cr0,0,r31,0             ; Compare Logical Immed
    2470: 4182 0010      1002480          bc  IF,cr0_EQ,lbc_3             ; Branch Conditional
    2474: 881F 0000                       lbz     r0,0(r31)               ; Load Byte and Zero
    2478: 2800 0000                       cmpli   cr0,0,r0,0              ; Compare Logical Immed
    247C: 4082 0048      10024C4          bc  IF_NOT,cr0_EQ,lbc_5         ; Branch Conditional
    2480: 881D 001C              lbc_3    lbz     r0,28(r29)              ; Load Byte and Zero
    2484: 9801 0038      3000038          stb     r0,vbc_1(SP)            ; Store Byte
    2488: 8801 0038      3000038          lbz     r0,vbc_1(SP)            ; Load Byte and Zero
    248C: 2800 003F                       cmpli   cr0,0,r0,63             ; Compare Logical Immed
    2490: 4081 000C      100249C          bc  IF_NOT,cr0_GT,lbc_4         ; Branch Conditional
    2494: 3800 003F                       li      r0,63                   ; Load Immed
    2498: 9801 0038      3000038          stb     r0,vbc_1(SP)            ; Store Byte
    249C: 3861 0039      3000039 lbc_4    la      r3,vbc_2(SP)            ; Load Address
    24A0: 389D 001D                       addi    r4,r29,29               ; Add Immed
    24A4: 88A1 0038      3000038          lbz     r5,vbc_1(SP)            ; Load Byte and Zero
    24A8: 4803 49F5      1036E9C          bl      proc1171                ; Branch , set LR
    24AC: 6000 0000                       nop                             ; No op
    24B0: 7FA3 EB78                       mr      r3,r29                  ; Move Reg
    24B4: 3881 0038      3000038          la      r4,vbc_1(SP)            ; Load Address
    24B8: 4800 3499      1005950          bl      proc79                  ; Branch , set LR
    24BC: 6000 0000                       nop                             ; No op
    24C0: 4800 0014      10024D4          b       lbc_6                   ; Branch
    24C4: 7FA3 EB78              lbc_5    mr      r3,r29                  ; Move Reg
    24C8: 7FE4 FB78                       mr      r4,r31
    24CC: 4800 3485      1005950          bl      proc79                  ; Branch , set LR
    24D0: 6000 0000                       nop                             ; No op
    24D4: 3860 0008              lbc_6    li      r3,8                    ; Load Immed
    24D8: 4803 48D9      1036DB0          bl      proc1166                ; Branch , set LR
    24DC: 6000 0000                       nop                             ; No op
    24E0: 2803 0000                       cmpli   cr0,0,r3,0              ; Compare Logical Immed
    24E4: 4182 000C      10024F0          bc  IF,cr0_EQ,lbc_7             ; Branch Conditional
    24E8: 4800 5F6D      1008454          bl      proc130                 ; Branch , set LR
    24EC: 6000 0000                       nop                             ; No op
    24F0: 83FD 02C0              lbc_7    lwz     r31,$2C0(r29)           ; Load Word and Zero
    24F4: 281F 0000                       cmpli   cr0,0,r31,0             ; Compare Logical Immed
    24F8: 4182 0028      1002520          bc  IF,cr0_EQ,lbc_8             ; Branch Conditional
    24FC: 807F 0014                       lwz     r3,20(r31)              ; Load Word and Zero
    2500: 3880 0000                       li      r4,0                    ; Load Immed
    2504: 38A0 FFFF                       li      r5,-1
    2508: 38C0 0001                       li      r6,1
    250C: 4801 E80D      1020D18          bl      proc566                 ; Branch , set LR
    2510: 6000 0000                       nop                             ; No op
    2514: 807F 0014                       lwz     r3,20(r31)              ; Load Word and Zero
    2518: 4802 B9E9      102DF00          bl      proc903                 ; Branch , set LR
    251C: 6000 0000                       nop                             ; No op
    2520: 807D 02CC              lbc_8    lwz     r3,$2CC(r29)            ; Load Word and Zero
    2524: 2803 0000                       cmpli   cr0,0,r3,0              ; Compare Logical Immed
    2528: 4182 0014      100253C          bc  IF,cr0_EQ,lbc_9             ; Branch Conditional
    252C: 8063 0014                       lwz     r3,20(r3)               ; Load Word and Zero
    2530: 3880 0001                       li      r4,1                    ; Load Immed
    2534: 4801 64F5      1018A28          bl      proc318                 ; Branch , set LR
    2538: 6000 0000                       nop                             ; No op
    253C: 8001 0098      3000098 lbc_9    lwz     r0,vbc_3(SP)            ; Load Word and Zero
    2540: 3821 0090                       la      SP,$90(SP)              ; Load Address
    2544: 7C08 03A6                       mtLR    r0                      ; Move To Special Purpose Reg
    2548: 83E1 FFFC                       lwz     r31,-4(SP)              ; Load Word and Zero
    254C: 83C1 FFF8                       lwz     r30,-8(SP)
    2550: 83A1 FFF4                       lwz     r29,-12(SP)
    2554: 4E80 0020                       blr                             ;  -> LR
HL Disassemble
v1.1
Buddy Ha©kit
26-Jul-1997

Notes:
Disassembled b20 example by Tony V., leader of the hotline hacking team.



    23E8: 7C08 02A6              proc28   mfLR    r0                      ; Move From Special Purpose Reg
    23EC: 93E1 FFFC                       stw     r31,-4(SP)              ; Store Word
    23F0: 93C1 FFF8                       stw     r30,-8(SP)
    23F4: 93A1 FFF4                       stw     r29,-12(SP)
    23F8: 9001 0008                       stw     r0,8(SP)
    23FC: 9421 FF70                       stwu    SP,-$90(SP)             ; Store Word with Update
    2400: 7C7D 1B78                       mr      r29,r3                  ; Move Reg
    2404: 7C9E 2378                       mr      r30,r4
    2408: 7CBF 2B78                       mr      r31,r5
    240C: 4800 014D      1002558          bl      proc29                  ; Branch , set LR
    2410: 6000 0000                       nop                             ; No op
    2414: 3800 002A                       li      r0,42                   ; Load Immed
    2418: B01D 0018                       sth     r0,24(r29)              ; Store Halfword
    241C: 387D 001C                       addi    r3,r29,28               ; Add Immed
    2420: 7FC4 F378                       mr      r4,r30                  ; Move Reg
    2424: 88BE 0000                       lbz     r5,0(r30)               ; Load Byte and Zero
    2428: 38A5 0001                       addi    r5,r5,1                 ; Add Immed
    242C: 4803 4A71      1036E9C          bl      proc1171                ; Branch , set LR
    2430: 6000 0000                       nop                             ; No op
    2434: 887E 0000                       lbz     r3,0(r30)               ; Load Byte and Zero
    2438: 3803 0005                       addi    r0,r3,5                 ; Add Immed
    243C: 901D 0220                       stw     r0,$220(r29)            ; Store Word
    2440: 3860 003A                       li      r3,58                   ; Load Immed
    2444: 389E 0001                       addi    r4,r30,1                ; Add Immed
    2448: 88BE 0000                       lbz     r5,0(r30)               ; Load Byte and Zero
    244C: 4803 4655      1036AA0          bl      proc1160                ; Branch , set LR
    2450: 6000 0000                       nop                             ; No op
    2454: 2803 0000                       cmpli   cr0,0,r3,0              ; Compare Logical Immed
    2458: 4182 000C      1002464          bc  IF,cr0_EQ,lbc_1             ; Branch Conditional
    245C: 3800 0000                       li      r0,0                    ; Load Immed
    2460: 4800 0008      1002468          b       lbc_2                   ; Branch
    2464: 3800 157C              lbc_1    li      r0,$157C                ; Load Immed
    2468: B01D 001A              lbc_2    sth     r0,26(r29)              ; Store Halfword
    246C: 281F 0000                       cmpli   cr0,0,r31,0             ; Compare Logical Immed
    2470: 4182 0010      1002480          bc  IF,cr0_EQ,lbc_3             ; Branch Conditional
    2474: 881F 0000                       lbz     r0,0(r31)               ; Load Byte and Zero
    2478: 2800 0000                       cmpli   cr0,0,r0,0              ; Compare Logical Immed
    247C: 4082 0048      10024C4          bc  IF_NOT,cr0_EQ,lbc_5         ; Branch Conditional
    2480: 881D 001C              lbc_3    lbz     r0,28(r29)              ; Load Byte and Zero
    2484: 9801 0038      3000038          stb     r0,vbc_1(SP)            ; Store Byte
    2488: 8801 0038      3000038          lbz     r0,vbc_1(SP)            ; Load Byte and Zero
    248C: 2800 003F                       cmpli   cr0,0,r0,63             ; Compare Logical Immed
    2490: 4081 000C      100249C          bc  IF_NOT,cr0_GT,lbc_4         ; Branch Conditional
    2494: 3800 003F                       li      r0,63                   ; Load Immed
    2498: 9801 0038      3000038          stb     r0,vbc_1(SP)            ; Store Byte
    249C: 3861 0039      3000039 lbc_4    la      r3,vbc_2(SP)            ; Load Address
    24A0: 389D 001D                       addi    r4,r29,29               ; Add Immed
    24A4: 88A1 0038      3000038          lbz     r5,vbc_1(SP)            ; Load Byte and Zero
    24A8: 4803 49F5      1036E9C          bl      proc1171                ; Branch , set LR
    24AC: 6000 0000                       nop                             ; No op
    24B0: 7FA3 EB78                       mr      r3,r29                  ; Move Reg
    24B4: 3881 0038      3000038          la      r4,vbc_1(SP)            ; Load Address
    24B8: 4800 3499      1005950          bl      proc79                  ; Branch , set LR
    24BC: 6000 0000                       nop                             ; No op
    24C0: 4800 0014      10024D4          b       lbc_6                   ; Branch
    24C4: 7FA3 EB78              lbc_5    mr      r3,r29                  ; Move Reg
    24C8: 7FE4 FB78                       mr      r4,r31
    24CC: 4800 3485      1005950          bl      proc79                  ; Branch , set LR
    24D0: 6000 0000                       nop                             ; No op
    24D4: 3860 0008              lbc_6    li      r3,8                    ; Load Immed
    24D8: 4803 48D9      1036DB0          bl      proc1166                ; Branch , set LR
    24DC: 6000 0000                       nop                             ; No op
    24E0: 2803 0000                       cmpli   cr0,0,r3,0              ; Compare Logical Immed
    24E4: 4182 000C      10024F0          bc  IF,cr0_EQ,lbc_7             ; Branch Conditional
    24E8: 4800 5F6D      1008454          bl      proc130                 ; Branch , set LR
    24EC: 6000 0000                       nop                             ; No op
    24F0: 83FD 02C0              lbc_7    lwz     r31,$2C0(r29)           ; Load Word and Zero
    24F4: 281F 0000                       cmpli   cr0,0,r31,0             ; Compare Logical Immed
    24F8: 4182 0028      1002520          bc  IF,cr0_EQ,lbc_8             ; Branch Conditional
    24FC: 807F 0014                       lwz     r3,20(r31)              ; Load Word and Zero
    2500: 3880 0000                       li      r4,0                    ; Load Immed
    2504: 38A0 FFFF                       li      r5,-1
    2508: 38C0 0001                       li      r6,1
    250C: 4801 E80D      1020D18          bl      proc566                 ; Branch , set LR
    2510: 6000 0000                       nop                             ; No op
    2514: 807F 0014                       lwz     r3,20(r31)              ; Load Word and Zero
    2518: 4802 B9E9      102DF00          bl      proc903                 ; Branch , set LR
    251C: 6000 0000                       nop                             ; No op
    2520: 807D 02CC              lbc_8    lwz     r3,$2CC(r29)            ; Load Word and Zero
    2524: 2803 0000                       cmpli   cr0,0,r3,0              ; Compare Logical Immed
    2528: 4182 0014      100253C          bc  IF,cr0_EQ,lbc_9             ; Branch Conditional
    252C: 8063 0014                       lwz     r3,20(r3)               ; Load Word and Zero
    2530: 3880 0001                       li      r4,1                    ; Load Immed
    2534: 4801 64F5      1018A28          bl      proc318                 ; Branch , set LR
    2538: 6000 0000                       nop                             ; No op
    253C: 8001 0098      3000098 lbc_9    lwz     r0,vbc_3(SP)            ; Load Word and Zero
    2540: 3821 0090                       la      SP,$90(SP)              ; Load Address
    2544: 7C08 03A6                       mtLR    r0                      ; Move To Special Purpose Reg
    2548: 83E1 FFFC                       lwz     r31,-4(SP)              ; Load Word and Zero
    254C: 83C1 FFF8                       lwz     r30,-8(SP)
    2550: 83A1 FFF4                       lwz     r29,-12(SP)
    2554: 4E80 0020                       blr                             ;  -> LR


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