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Motorola 68000
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In 1979, Motorola introduced the MC68000 microprocessor. Although the Mac was not the first computer to use the chip (computers such as the Apple Lisa and Xerox Star also ran on this graphically-oriented chip), the Macintosh’s future was firmly tied to it when it was selected as the brains for the Macintosh.
The 68000 processor seems very antiquated today with its 68,000 transistors and its hybrid 16- and 32-bit buses, but at the time of its development it was leading-edge. The processor could handle information internally in 32-bit chunks, although it transferred its data back to RAM or I/O in 16-bit chunks. The 68000 did not have room for cache memory, and ran at 16.67 MHz.
Features of the MC68000[edit]
The MC68000 processor has seventeen 32-bit internal registers, a 32-bit program counter, and a 16-bit status register. Instructions can use data up to 32 bits long. The external data bus is 16 bits wide, so for every 32-bit longword read or written, the MC68000 must perform two data transfers.
The MC68000 provides 56 different instruction types with 14 addressing modes. Each of these instructions is fairly simple, causing a transfer of data from the data bus into a register, for example, or adding the data in two registers. Each valid combination of instruction type and addressing mode is represented in machine language by a binary number.
The MC68000 can handle both asynchronous and synchronous data transfers. Synchronous data transfers are required for devices designed to work with the MC6800, the predecessor of the MC68000 microprocessor.
Asynchronous data transfers are controlled by several signals, including a Data Transfer Acknowledge signal (/DTACK), which indicates that a data transfer is complete. The processor also can assert a Read/Write signal (R/W) and upper and lower data strobes (/UDS and /LDS). In the MC68000, the /UDS and /LDS signals together serve as the external A0 address signal: when /UDS is asserted, A0 is considered to be 0, and when /LDS is asserted, A0 is considered to be 1. Therefore, even-addressed byte-wide reads and writes use the upper byte of the data bus and odd-addressed accesses use the lower byte of the data bus. Synchronous data transfers are controlled by a set of three signals: the Enable (E) signal, also called the E clock, which times the data transfer; the Valid Peripheral Address (/VPA) signal, which indicates that the device addressed requires synchronous communication; and the Valid Memory Address (/VMA) signal, which indicates that there is a valid address on the address bus.
The /DTACK and /VPA signals are generated by the general logic circuits, which handle all handshaking between the main processor and internal devices.
he MC68000 microprocessor provides bus arbitration signals that enable it to share its external address and data buses with other microprocessors. Although no coprocessors share the processor buses in the Macintosh Portable, Macintosh SE, or classic Macintosh computers, developers have taken advantage of the bus arbitration capability to design accelerator cards for these computers.
At any given time, the MC68000 operates in one of two states: the user state or the supervisor state. Certain instructions, such as the Reset instruction, cannot be executed in the user state. The purpose of this design is to prevent application programs from accessing information or executing instructions that affect the operating system or other programs that might be running at the same time. Not all operating systems take advantage of this feature.
Normal sequential processing of instructions can be interrupted through the exception mechanism. Exceptions include resets and interrupts, which are hardware signals, and traps, which result from the execution of instructions. When the MC68000 detects an exception, it jumps to code pointed to by an exception vector. The lower 1 KB of address space of the Mc6sooo is reserved for up to 255 exception vectors. The use of MC68000 interrupts in Macintosh computers is described in the following section.
MC68000 interrupts[edit]
The MC68000 has three interrupt lines- /IPL0, /IPL1, and /IPL2- providing seven levels of interrupt priority. The status register in the MC68000 has a 3-bit field that indicates the current processor priority level; interrupts with a priority level equal to or lower than the current processor priority level are ignored.
When a signal is received over one or more interrupt lines, the main processor determines the priority of the interrupt and, if the interrupt priority is higher than the current processor priority (set by the software), the processor suspends execution of the currently running program.
The Macintosh computers use automatic vectoring for interrupts. The MC68000 acknowledges an interrupt by putting an address in the range $FF FFF0 through $FF FFFF on the address bus. The general logic circuits respond by asserting the Valid Peripheral Address (/VPA) signal, which causes the main processor to generate a vector number based on the level of the interrupt. The processor then jumps to the interrupt handler at the address calculated by multiplying the vector number by 4.
There are three interrupt sources in the Macintosh Plus and earlier Macintosh computers: the VIA, the SCC, and the programmer's interrupt switch. In the Macintosh SE, the SCSI controller can also generate an interrupt. The SCC interrupt and the programmer's interrupt switch are connected to their own separate MC68000 interrupt lines, and the VIA and SCSI both can cause an interrupt on the third processor interrupt line. In the Macintosh Portable computer, the SCSI IRQ line goes to the VIA; the ASC is connected to an MC68HC000 interrupt line. The programmer's interrupt switch in the Macintosh Portable is connected to the Miscellaneous GLU custom IC, which is connected to an MC68HC000 interrupt line.
The lowest level interrupts in the classic Macintosh computers are generated by the VIA. The interrupt request line from the VIA goes to the PALs, which can assert an interrupt to the processor on line /IPL0. The PALs also monitor interrupt line /IPL1, and deassert /IPL0 whenever /IPL1 is asserted.
Several different events can cause the VIA to generate an interrupt request, including timeouts by the VIA timers, keyboard transactions, the start of the video display's vertical blanking interval, and the one-second tick from the real-time clock. To determine which device caused a VIA interrupt, the processor must read the VIA's Interrupt Flag register at vBase+vIFR.
Intermediate-level interrupts are generated by the SCC. The SCC interrupt output is connected directly to the MC68000's /IPL1 line. Sending or receiving serial port data, various handshaking events, and mouse motion events can cause the SCC to generate an /IPL1 interrupt. See the documentation for the Zilog Z8530 IC for details about the sources of interrupts and the software controls over those interrupts.
The highest-level interrupts in the classic Macintosh computers are generated by the programmer's interrupt switch (which the user can install, together with the Reset switch, at the left side of the Macintosh). This switch is connected directly to the MC68000's /IPL2 line. The programmer's switch is used as an aid to debugging programs; it allows a programmer to interrupt an executing program without resetting the computer. The programmer's switch generates level-4 interrupts, which can be inhibited by the MC68000's interrupt priority mask; you cannot generate nonmaskable (level-7) interrupts on the classic Macintosh computers.
Note: Although the Macintosh Plus contains an NCR 5380 SCSI controller IC, the IRQ and DRQ interrupt signals provided by that IC do not generate MC68000 interrupts in the Macintosh Plus. Software must poll the SCSI controller's Bus and Status register to determine whether a SCSI interrupt is pending.
The lowest level interrupts in the Macintosh SE can be generated by either the VIA or the SCSI IRQ line or both; these interrupt requests are connected to the BBU, which can assert an interrupt to the processor on line /IPL0. To determine which source has generated the /IPL0 interrupt, the software must poll both sources. However, software can set a bit in the VIA that causes the SCSI interrupt to be masked, that is, that prevents the SCSI interrupt from being passed on to the MC68000. When this mask bit is set to 1, only the VIA can originate an /IPL0 interrupt. The BBU also monitors interrupt line /IPL1 and deasserts /IPL0 whenever /IPL1 is asserted.
Note: The SCSI controller can generate two types of interrupt requests: IRQ interrupts-which can be used to indicate error conditions on the SCSI bus-and DRQ interrupts, which the SCSI can assert when the first byte of a block of data is ready to be transferred. The DRQ interrupt signal provided by the SCSI controller does not generate an MC68000 interrupt in the Macintosh SE. Software in the Macintosh SE must poll the SCSI controller's Bus and Status register to determine whether a SCSI DRQ interrupt is pending. For more information about the various NCR 5380 interrupt conditions and about software control over these interrupts, see the NCR 5380 manual.
Several different events can cause the VIA to generate an interrupt request, including timeouts on the VIA timers, transactions on the Apple Desktop Bus, the video display's vertical blanking, and the one-second tick from the real-time clock. Software can enable or disable any of these interrupts by setting bits in the VIA's Interrupt Enable register. To determine which device caused a VIA interrupt, the processor must read the VIA's Interrupt Flag register.
Intermediate-level interrupts are generated by the SCC. The SCC interrupt output is connected directly to the MC68000's /IPL1 line. Sending or receiving serial port data and various handshaking events can cause the SCC to generate an /IPL1 interrupt. See the Zilog 8530 manual for details about the sources of interrupts and the software controls over those interrupts.
The highest-level interrupt in the Macintosh SE is generated by the programmer's interrupt switch, which is connected directly to the MC68000's /IPL2 line. The programmer's switch generates a level-4 interrupt, which can be inhibited by the MC68000's interrupt priority mask. You cannot generate nonmaskable (level-7) interrupts on the Macintosh SE computer.
The lowest level interrupts in the Macintosh Portable are generated by the VIA. The interrupt request line from the VIA goes to the CPU GLU custom IC, which can assert an interrupt to the processor on line /IPL0. The CPU GLU also monitors interrupt line /IPL1, and deasserts /IPL0 whenever /IPL1 is asserted. Notice that, whereas in the Macintosh SE, the SCSI IRQ line is connected to the general logic circuits, in the Macintosh Portable, that line is connected to the VIA.
Several different devices can cause the VIA in the Macintosh Portable to generate an /IPL0 interrupt, including the SCSI controller (through its IRQ line), the Power Manager IC, the VIA timers, Apple Desktop Bus, the video display circuitry (vertical blanking signal), and the real-time clock. Software can enable or disable any of these interrupts by setting bits in the VIA's Interrupt Enable register. To determine which device caused a VIA interrupt, the processor must read the VIA's Interrupt Flag register.
Intermediate-level interrupts are generated by either the SCC or the ASC, both of which are connected directly to the MC68HC000's /IPL1 line. Sending or receiving serial port data and various handshaking events can cause the SCC to generate an /IPL1 interrupt. See the Zilog 8530 manual for details about the sources of SCC interrupts and the software controls over those interrupts. The ASC generates an interrupt when the sound buffers are half empty and when they are completely empty. ASC interrupts are handled by the Sound Manager.
The highest-level interrupts are generated by the Miscellaneous GLU IC in response to an interrupt request from the programmer's interrupt switch (which the user can install, together with the Reset switch, at the left side of the computer). The programmer's switch (through the Misc. GLU) generates level-4 interrupts; you cannot generate nonmaskable (level-7) interrupts on the Macintosh Portable computer.
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