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Motorola 68030

From Higher Intellect Vintage Wiki

In 1987, Motorola introduced the 68030. This chip was not much faster than the 68020, but offered design innovations, such as a built-in Paged-Memory Management Unit (PMMU) that provided support for System 7’s virtual memory. Apple incorporated the 68030 into its second generation Macintosh II line of computers: The Macintosh IIx, IIcx, IIci, IIvi, IIvx, Performa 400 and 600, and SE/30, as well as most of the first generation PowerBooks (the 145, 170, 180, and so forth).

One notable change between this processor and the Motorola 68020 processor is the addition of an MMU allowing the 68030 to work with virtual memory. The 68030 was used in a number of Apple Computer systems along with Amiga, Sun, NeXT.

The 68030 added a 256-byte data cache to the existing instruction cache to hold the most recently used data which can be sent to the CPU without calling on RAM or disk.

The 68030 introduced a parallel bus design, called the Harvard-style bus architecture, that consisted of two 32-bit address and data buses. The address and data buses operate in parallel, letting the CPU perform multiple tasks simultaneously. Using this bus design, the CPU can simultaneously access its data and instruction caches, as well as external memory simultaneously.

Replaced by the Motorola 68040 and Motorola 68LC040 (without the FPU).

MC68030 enhancements[edit]

To an application program running in the user state, the MC68030 appears identical to an MC68020: it has sixteen 32-bit data and address registers, five special-purpose control registers, a 32-bit program counter, and a 16-bit status register. Instructions can use data up to 32 bits long. To a system program running in the supervisor state, on the other hand, the MC68030 offers several enhancements, including five additional special-purpose control registers and an additional status register.

The MC68030 has a data cache in addition to the instruction cache found in the MC68020 . The MC68030 checks the data cache to determine if the operand required for an instruction is in the cache before performing a read. When the operand is found in the cache, the operation is much faster than it is when the fetch has to be made from external memory.

The MC68030 has an on-chip memory management unit (MMU), which replaces the Address Management Unit (AMU) or the MC68851 Paged Memory Management Unit (PMMU) used with the MC68020 in the Macintosh II. Having the MMU built into the main processor saves one wait state over the use of an external MMU such as that in the Macintosh II. To control the internal MMU, the MC68030 has four instruction types not supported by the MC68020; these instructions are a subset of the instruction set provided by the MC68851 MMU. The MC68030's MMU can be programmed to perform an address translation- such as the 24-bit to 32-bit address translation required by the Macintosh operating system- or to act as a paged memory management unit to support virtual memory.

MC68030 interrupts[edit]

The MC68030-based Macintosh computers- Macintosh SE/30, Macintosh IIx, Macintosh IIcx, Macintosh IIci, and Macintosh IIfx- handle interrupts in much the same way as they are handled by the Macintosh II; the sources and levels of interrupts in the MC68030-based computers are similar to those in the Macintosh II computer. As in the current Macintosh II, the power-off switch in an MC68030-based computer is connected directly to hardware and does not generate an interrupt.

In addition to the interrupt requests from the SCSI, ASC, and NuBus, there are several other possible sources of VIA interrupts, including the VIA timers, Apple Desktop Bus transactions, the Vertical Blanking signal (VBL), and the one-second tick from the real- time clock. To determine which device caused a VIA interrupt, the processor must read the VIA's Interrupt Flag register.

The SCSI can generate two types of interrupt requests: IRQ interrupts-which can be used to indicate error conditions on the SCSI bus-and DRQ interrupts, which the SCSI can use to interrupt the processor when the first byte of a block of data is ready to be transferred. Both of these interrupts can be enabled or disabled by setting bits in the Interrupt Enable register inside VIA2 (RBV in the Macintosh IIci, OSS in the Macintosh IIfx). For more information about the SCSI controller's various interrupt conditions and about software control over those interrupts, see the reference manual for the NCR 5380.

The ASC can also generate an interrupt request. As for the SCSI interrupt requests , this interrupt can be enabled or disabled by setting a bit in the Interrupt Enable register.

Each NuBus slot can generate an interrupt request. In the Macintosh IIx and Macintosh IIcx computers, the GLUE IC performs an OR operation on all the NuBus interrupt lines and sends the result to an interrupt request line on VIA2. Each of the NuBus slot interrupt lines is also connected to a data input of VIA2. When the main processor receives an interrupt, it polls the Interrupt Flag register in VIA2 to determine the source and, if the interrupt was caused by a NuBus slot, the main processor then polls VIA2 Data register A to determine which slot was the source.

The NuBus slots in the Macintosh IIci and the Macintosh IIfx generate interrupt requests in the same way as the slots on the Macintosh IIx but the hardware that handles them is different. In the Macintosh IIci, the functions of the GLUE are incorporated into the RBV along with VIA2-emulation registers including the Interrupt Flag register. Similarly, in the Macintosh IIfx, the OSS performs both the recording of the interrupts from the individual slots and the OR operation that produces the slot IRQ. When the main processor in one of these machines receives an interrupt, it polls the Interrupt Flag registers in the RBV or the OSS to determine the source.

In the Macintosh SE/30 computer, the processor-direct slot (PDS) connector provides lines for the first three interrupt-request lines to the GLUE IC, so an expansion card can emulate a NuBus card in any of the first three NuBus slots (slots $9 , $A , or $B) . The video circuitry, which emulates a NuBus card in slot $E, generates an interrupt request to the GLUE IC on the last interrupt-request line (lines 4 and 5 are not used). In addition, the expansion connector is connected directly to the three MC68030 interrupt lines, for use by expansion cards that do not emulate NuBus cards.

The SCC's interrupt output is connected directly to the general-logic IC- the GLUE in the Macintosh IIx and Macintosh IIcx, RBV in the Macintosh IIci, or OSS in the Macintosh IIfx. Sending or receiving serial port data and various handshaking events can cause the SCC to generate an interrupt. See the Zilog 8530 manual for details about the sources of SCC interrupts and the software controls over those interrupts.

The highest-level interrupts are generated by the programmer's interrupt switch. This switch is connected directly to the general-logic IC- the GLUE in the Macintosh IIx and Macintosh IIcx, RBV in the Macintosh IIci, or OSS in the Macintosh IIfx. The programmer's switch generates level-7 interrupts, which cannot be inhibited by the MC68030's interrupt priority mask.