Number Nine Imagine 128 Series 2 Chip
The Imagine 128 Series 2 is the second generation in the Imagine family of high performance visual processors. It is implemented in a 0.5 micron 3.3 volt CMOS gate array process. Packaged in a 352 PBGA, (Plastic Ball Grid Array), it provides increased performance and added functionality over its predecessor the Imagine 128 with reduced overall system cost.
The Imagine 128 Series 2 provides a high performance PCI 2.1 compliant interface with no additional external logic required. The Drawing Engine commands provide all of the normally required operations including: BIT BLT, Line, Triangle, Write Image, and Read Image. Software may interact with the Imagine 128 Series 2 by directly manipulating pixels through the Memory Windows interface.
The Imagine 128 Series 2 is implemented using a symmetric multi graphic processor (SMGP) architecture. This architecture allows the execution of two drawing commands simultaneously with totally independent parameters.
- 33 MHz PCI 2.1 host interface clock.
- Asynchronous graphic processor.
- EDO Memory controller.
- Integrated VGA.
- Integrated display list processor.
- Integrated display controller (for DRAM frame buffers).
- Integrated Color space converter.
- Integrated DIB Converter.
- Directly supports 8, 16, 32 bits per pixel
- Two Operand Bit Blts.
- Scaling with X and Y interpolation.
- Flat and shaded line drawing with patterning.
- Flat and Gouraud shaded patterned triangles.
- Shared Z buffer, frame buffer, and back buffer.
- Hardware three dimensional volume clipping.
- Sixteen bit logical addressing in both X and Y, and 32 bits in Z.
- Two configurable Memory Windows.
- High speed image transfer.