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PowerPC 604
Developed as part of the Apple/IBM/Motorola alliance. The 604 was used in a number of Apple Computer systems, some IBM RS/6000 models and other systems/applications. This CPU is also used in the Motorola Atlas system.
General Information
The principal features of the PowerPC 604 microprocessor include
- full RISC processing architecture
- parallel processing units: one load-store unit, two integer units, one complex integer unit, and one floating-point unit
- a branch manager that can usually implement branches by reloading the incoming instruction queue without using any processing time
- an internal memory management unit (MMU)
- separate built-in caches for data and instructions, 16 KB each, four-way set associative
The 604 processor is the first chip that is able to issue four instructions in parallel (as compared to the three-way pipeline of the 601 and 603 chips)—a very high level of superscalar performance. In fact, the 604 actually has a six-way pipeline that can execute and retire up to six instructions simultaneously: a floating-point unit (FPU), a branch-processing unit (BPU), a load/store unit (LSU), and three integer units (IUs). The three IUs are set up so that two can process single-cycle instructions and the third handles multiple-cycle instructions. This design makes the 604 the fastest integer and float-point processing computer on the market.
The 604 has redesigned the unified cache of the 601 to create a separate 16K data cache and a 16K instruction cache for better CPU throughput. The instruction cache can issue four instructions per clock cycle while the data cache supplies two words (each word being eight bytes) per cycle. The 604 also uses functional units to manage the flow of instructions through the processor and execution units to further increase its efficiency.
The 604 processor contains 3.6 million transistors on a 196 square-millimeter wafer and can operate at 3.3 volts. It also contains a nap mode like the 603 for power savings. Because of the number of transistors available, the 604 chip contains all of the 32-bit instructions defined by IBM’s PowerPC architecture.
PowerPC 604e
Improves performance over the 604 with additional L1 cache and faster clock speeds.
In 1995, Motorola and IBM announced an extended version of the 604 chip, called the 604e processor. This processor is for use in high-performance power Macs and for upgrades to existing 601 Power Macs. The 604e achieves 150 MHz speeds, yet is smaller and operates cooler than the 604. The new .35- micron fabrication technology allows IBM and Motorola to pack more transistors into a smaller space. The 604e returns to the concept of a unified cache, only double the size of the 601’s cache at 64K. This 64K data and instruction cache improves the performance of 68K Mac emulation.