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The early [[MIPS]] architectures were 32-bit implementations (generally 32-bit wide registers and data paths), while later versions were 64-bit implementations. Five backward-compatible revisions of the MIPS instruction set exist, named <tt>MIPS I</tt>, <tt>MIPS II</tt>, <tt>MIPS III</tt>, <tt>MIPS IV</tt>, and <tt>MIPS 32/64</tt>. The latest of these, <tt>MIPS 32/64</tt> Release 2, defines a control register set as well as the instruction set. Several "add-on" extensions are also available, including <tt>MIPS-3D</tt> which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, <tt>MDMX(MaDMaX)</tt> which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, <tt>MIPS16</tt> which adds compression to the instruction stream to make programs take up less room (allegedly a response to the ARM architecture encoding in the ARM architecture), and the recent addition of <tt>MIPS MT</tt>, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors.
 
The early [[MIPS]] architectures were 32-bit implementations (generally 32-bit wide registers and data paths), while later versions were 64-bit implementations. Five backward-compatible revisions of the MIPS instruction set exist, named <tt>MIPS I</tt>, <tt>MIPS II</tt>, <tt>MIPS III</tt>, <tt>MIPS IV</tt>, and <tt>MIPS 32/64</tt>. The latest of these, <tt>MIPS 32/64</tt> Release 2, defines a control register set as well as the instruction set. Several "add-on" extensions are also available, including <tt>MIPS-3D</tt> which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, <tt>MDMX(MaDMaX)</tt> which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, <tt>MIPS16</tt> which adds compression to the instruction stream to make programs take up less room (allegedly a response to the ARM architecture encoding in the ARM architecture), and the recent addition of <tt>MIPS MT</tt>, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors.
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Because the designers created such a [[#Summary of R3000 instruction set|clean instruction set]], computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the [[MIPS]] CPU family greatly influenced later RISC architectures such as DEC Alpha.
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Because the designers created such a [[#Summary of R3000 instruction set|clean instruction set]], computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the [[MIPS]] CPU family greatly influenced later RISC architectures such as [[DEC Alpha]].
    
==History==
 
==History==

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