Please consider a donation to the Higher Intellect project. See https://preterhuman.net/donate.php or the Donate to Higher Intellect page for more info.

Changes

Jump to navigation Jump to search
no edit summary
Line 486: Line 486:  
The R18000 improved the floating-point instruction queues and revised the floating-point unit to feature two multiply-add units, quadrupling the peak FLOPS count. Division and square-root were performed in separate non-pipelined units in parallel to the multiply-add units. The system interface and memory hierarchy was also significantly reworked. It would have a 52-bit virtual address and a 48-bit physical address. The bidirectional multiplexed address and data system bus of the R18000 would be replaced by two unidirectional DDR links, a 64-bit multiplexed address and write path and a 128-bit read path. Although they are unidirectional, each path could be shared by another R18000, although the two would be shared through multiplexing. The bus could also be configured in the SysAD or Avalanche configuration for backwards compatibility with R10000 systems.
 
The R18000 improved the floating-point instruction queues and revised the floating-point unit to feature two multiply-add units, quadrupling the peak FLOPS count. Division and square-root were performed in separate non-pipelined units in parallel to the multiply-add units. The system interface and memory hierarchy was also significantly reworked. It would have a 52-bit virtual address and a 48-bit physical address. The bidirectional multiplexed address and data system bus of the R18000 would be replaced by two unidirectional DDR links, a 64-bit multiplexed address and write path and a 128-bit read path. Although they are unidirectional, each path could be shared by another R18000, although the two would be shared through multiplexing. The bus could also be configured in the SysAD or Avalanche configuration for backwards compatibility with R10000 systems.
   −
The R18000 would have a 1 MB four-way set-associative secondary cache would be included on-die; supplemented by an optional tertiary cache built from single data rate (SDR) or double data rate (DDR) SSRAM or DDR SDRAM with capacities of 2 to 64 MB. The L3 cache had its cache tags, equivalent to 400 KB, located on-die to reduce latency. The L3 cache is accessed via a 144-bit bus, of which 128 bits are for data and 8 bit for ECC. The L3 cache's clock rate was to have been programmable.
+
The R18000 would have a 1 MB four-way set-associative secondary cache would be included on-die; supplemented by an optional tertiary cache built from single data rate (SDR) or double data rate ([[DDR]]) SSRAM or DDR [[SDRAM]] with capacities of 2 to 64 MB. The L3 cache had its cache tags, equivalent to 400 KB, located on-die to reduce latency. The L3 cache is accessed via a 144-bit bus, of which 128 bits are for data and 8 bit for ECC. The L3 cache's clock rate was to have been programmable.
    
The R18000 was to be fabricated in NEC's UX5 process, a 0.13 µm CMOS process with nine levels of copper interconnect. It would have used 1.2 V power supply and dissipated less heat than contemporary server microprocessors in order to be densely packed into systems.
 
The R18000 was to be fabricated in NEC's UX5 process, a 0.13 µm CMOS process with nine levels of copper interconnect. It would have used 1.2 V power supply and dissipated less heat than contemporary server microprocessors in order to be densely packed into systems.
Line 530: Line 530:  
[[Category:SGI]][[Category:Computing]]
 
[[Category:SGI]][[Category:Computing]]
 
[[Category:Processors]]
 
[[Category:Processors]]
 +
[[Category:MIPS]]

Navigation menu