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==PCI Bus Bridge==
 
==PCI Bus Bridge==
 
The PSX+ IC acts as a bridge between the processor bus and the [[PCI]] expansion bus, converting signals on one bus to the equivalent signals on the other bus. The PCI bridge functions are performed by two converters. One accepts requests from the processor bus and presents them to the PCI bus. The other converter accepts requests from the PCI bus and provides access to the RAM and ROM on the processor bus.
 
The PSX+ IC acts as a bridge between the processor bus and the [[PCI]] expansion bus, converting signals on one bus to the equivalent signals on the other bus. The PCI bridge functions are performed by two converters. One accepts requests from the processor bus and presents them to the PCI bus. The other converter accepts requests from the PCI bus and provides access to the RAM and ROM on the processor bus.
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The PCI bus bridge in the PSX+ IC runs asynchronously so that the processor bus and the PCI bus can operate at different rates. The processor bus operates at a clock rate of 50 MHz and the PCI bus operates at 33 MHz.
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The PCI bus bridge generates PCI parity as required by the PCI bus specification, but it does not check parity or respond to the parity error signal.
    
=See Also=
 
=See Also=
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[[Category:Apple]]
 
[[Category:Apple]]
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[[Category:Definitions]]

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