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===Madison===
 
===Madison===
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Madison was initially introduced on June 30, 2003.  It was initially available in three versions: 1.3 GHz with 3 MiB of cache, 1.4 GHz with 4 MiB of cache and 1.5 GHz with 6 MiB of cache. Manufactured in a 130 nm process, it had a die size of 374 mm². Its power envelope remained unchanged from McKinley at 130 watts. On September 8, 2003, a 1.4 GHz version with 1.5 MiB of cache was released. 1.4 GHz and 1.6 GHz versions with 3 MiB of cache were launched on April 13, 2004. November 8, 2004 saw the release of the first processor in the Madison 9M series, at 1.6 GHz with 9 MiB of cache. On July 18, 2005, more variations of the Madison 9M were introduced, including 1.67 GHz models with a 333 MHz FSB and either 6 MiB or 9 MiB of cache. On introduction, the latter part set a record SPECfp2000 result of 2,801<ref>[http://www.spec.org/cpu2000/results/res2005q3/cpu2000-20050628-04342.html]
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Madison was initially introduced on June 30, 2003.  It was initially available in three versions: 1.3 GHz with 3 MiB of cache, 1.4 GHz with 4 MiB of cache and 1.5 GHz with 6 MiB of cache. Manufactured in a 130 nm process, it had a die size of 374 mm². Its power envelope remained unchanged from McKinley at 130 watts. On September 8, 2003, a 1.4 GHz version with 1.5 MiB of cache was released. 1.4 GHz and 1.6 GHz versions with 3 MiB of cache were launched on April 13, 2004. November 8, 2004 saw the release of the first processor in the Madison 9M series, at 1.6 GHz with 9 MiB of cache. On July 18, 2005, more variations of the Madison 9M were introduced, including 1.67 GHz models with a 333 MHz FSB and either 6 MiB or 9 MiB of cache. On introduction, the latter part set a record SPECfp2000 result of 2,801 in a Hitachi, Ltd. Computing blade.
Result submitted to SPEC on June 13, 2005 by Hitachi</ref> in a Hitachi, Ltd. Computing blade.
      
In January 2005 OpenVMS was added to the line up of Operating Systems able to run on these processors.
 
In January 2005 OpenVMS was added to the line up of Operating Systems able to run on these processors.
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===Montecito===
 
===Montecito===
The Dual-Core Intel Itanium 2 processor 9000 series (code-named Montecito) was released on July 18, 2006. Montecito is the first Itanium processor to have two cores per die. It was originally planned to feature advanced power and thermal management improvements. However, the originally planned ''Foxton'' dynamic clock speed feature was removed due to unspecified engineering issues (it is under consideration by Intel for inclusion in future Itanium 2 processor versions). Despite the elimination of this feature, Intel reports that Montecito doubles the performance of its single-core predecessor, while reducing power consumption by approximately 20 percent. <ref>[http://www.intel.com/products/processor/itanium2/index.htm] Intel product announcement</ref> It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization. Manufactured in a 90nm process, Montecito debuted with speeds between 1.4 GHz for a low-power configuration and 1.6 GHz / 12 + 12 MiB L3 at the high end. The front side bus runs at 400 MHz and 533 MHz.
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The Dual-Core Intel Itanium 2 processor 9000 series (code-named Montecito) was released on July 18, 2006. Montecito is the first Itanium processor to have two cores per die. It was originally planned to feature advanced power and thermal management improvements. However, the originally planned ''Foxton'' dynamic clock speed feature was removed due to unspecified engineering issues (it is under consideration by Intel for inclusion in future Itanium 2 processor versions). Despite the elimination of this feature, Intel reports that Montecito doubles the performance of its single-core predecessor, while reducing power consumption by approximately 20 percent. It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization. Manufactured in a 90nm process, Montecito debuted with speeds between 1.4 GHz for a low-power configuration and 1.6 GHz / 12 + 12 MiB L3 at the high end. The front side bus runs at 400 MHz and 533 MHz.
    
==Upcoming revisions==
 
==Upcoming revisions==
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Few details are known, other than the existence of the codename.
 
Few details are known, other than the existence of the codename.
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== References ==
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<references/>
      
==External links==
 
==External links==

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