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==High-end Server market==
 
==High-end Server market==
In recent years, SGI has continued to enhance its line of servers (of which the higher-end models are actually supercomputers) based around the SN architecture. SN, for Scalable Node, is a technology developed by SGI in the mid-1990s. SN is an example of [[CcNUMA|CC-NUMA]]: Cache-coherent Non-uniform memory access. In an SN system, processors, memory, and a bus- and memory-controller are coupled together into an entity known as a node. A node is usually a single circuit board. Nodes are connected via a high-speed interconnect originally called [[CrayLink]], since renamed [[NUMAlink]]. The result is a system that has no internal bus whatsoever. Rather, access between processors, memory, and I/O devices is facilitated through a switched fabric of links and routers. SN systems scale along several axes at once: as CPU count increases, so does memory capacity, I/O capacity, and system bisection bandwidth. The scalability of SN systems is a result of the cache-coherence of its distributed shared memory. This allows the combined memory of all the nodes to be accessed under a single OS image using standard shared-memory synchronization methods. This makes an SN system far easier to program and able to achieve a higher sustained vs peak performance ratio than non-cache-coherent systems like conventional clusters or massively parallel computers which require applications code to be written (or re-written) to do explicit message-passing communication between their nodes.
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In recent years, SGI has continued to enhance its line of servers (of which the higher-end models are actually supercomputers) based around the SN architecture. SN, for Scalable Node, is a technology developed by SGI in the mid-1990s. SN is an example of [[CcNUMA|CC-NUMA]]: Cache-coherent Non-uniform memory access. In an SN system, processors, memory, and a bus- and memory-controller are coupled together into an entity known as a node. A node is usually a single circuit board. Nodes are connected via a high-speed interconnect originally called CrayLink, since renamed [[NUMAlink]]. The result is a system that has no internal bus whatsoever. Rather, access between processors, memory, and I/O devices is facilitated through a switched fabric of links and routers. SN systems scale along several axes at once: as CPU count increases, so does memory capacity, I/O capacity, and system bisection bandwidth. The scalability of SN systems is a result of the cache-coherence of its distributed shared memory. This allows the combined memory of all the nodes to be accessed under a single OS image using standard shared-memory synchronization methods. This makes an SN system far easier to program and able to achieve a higher sustained vs peak performance ratio than non-cache-coherent systems like conventional clusters or massively parallel computers which require applications code to be written (or re-written) to do explicit message-passing communication between their nodes.
    
The first SN system, known as SN-0, was released in 1996 as the Origin family. Based on the MIPS [[R10000]] processor, the Origin 200 scaled from one to four processors, and the Origin 2000 scaled from two to 128 processors. Later enhancements to the Origin 2000 line enabled systems of as large as 512 processors.
 
The first SN system, known as SN-0, was released in 1996 as the Origin family. Based on the MIPS [[R10000]] processor, the Origin 200 scaled from one to four processors, and the Origin 2000 scaled from two to 128 processors. Later enhancements to the Origin 2000 line enabled systems of as large as 512 processors.

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