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The '''R10000''', code-named "T5", is a microprocessor implementation of the [[MIPS IV]] instruction set architecture (ISA) developed by [[MIPS Technologies|MIPS Technologies, Inc.]] (MTI), then a division of [[Silicon Graphics|Silicon Graphics, Inc.]] (SGI). The chief designers were Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture was known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaced the [[R8000]] in the high-end and the [[R4400]] elsewhere. MTI was a fabless semiconductor company, the R10000 was fabricated by NEC and Toshiba]. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400. <!--Inaccurate?: It was originally intended to be the last high-performance, non-embedded MIPS microprocessor to be developed for SGI, who had opted to replace MIPS with the [[Itanium]]. Due to Itanium experiencing repeated delays, the R10000's basic microarchitecture became the basis for successive derivatives to maintain the design's competitiveness.-->
 
The '''R10000''', code-named "T5", is a microprocessor implementation of the [[MIPS IV]] instruction set architecture (ISA) developed by [[MIPS Technologies|MIPS Technologies, Inc.]] (MTI), then a division of [[Silicon Graphics|Silicon Graphics, Inc.]] (SGI). The chief designers were Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture was known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaced the [[R8000]] in the high-end and the [[R4400]] elsewhere. MTI was a fabless semiconductor company, the R10000 was fabricated by NEC and Toshiba]. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400. <!--Inaccurate?: It was originally intended to be the last high-performance, non-embedded MIPS microprocessor to be developed for SGI, who had opted to replace MIPS with the [[Itanium]]. Due to Itanium experiencing repeated delays, the R10000's basic microarchitecture became the basis for successive derivatives to maintain the design's competitiveness.-->
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== History ==
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== R10000 History ==
    
The R10000 was introduced in January 1996 at clock frequencies ranging from 150 MHz to 200 MHz, but was not available in large volumes until later in the year due to fabrication problems at MIPS's foundries. The 200 MHz version was in short supply throughout 1996, and was priced at US$3,000 as a result.
 
The R10000 was introduced in January 1996 at clock frequencies ranging from 150 MHz to 200 MHz, but was not available in large volumes until later in the year due to fabrication problems at MIPS's foundries. The 200 MHz version was in short supply throughout 1996, and was priced at US$3,000 as a result.

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