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The early [[MIPS]] architectures were 32-bit implementations (generally 32-bit wide registers and data paths), while later versions were 64-bit implementations. Five backward-compatible revisions of the MIPS instruction set exist, named <tt>MIPS I</tt>, <tt>MIPS II</tt>, <tt>MIPS III</tt>, <tt>MIPS IV</tt>, and <tt>MIPS 32/64</tt>. The latest of these, <tt>MIPS 32/64</tt> Release 2, defines a control register set as well as the instruction set. Several "add-on" extensions are also available, including <tt>MIPS-3D</tt> which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, <tt>MDMX(MaDMaX)</tt> which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, <tt>MIPS16</tt> which adds compression to the instruction stream to make programs take up less room (allegedly a response to the ARM architecture encoding in the ARM architecture), and the recent addition of <tt>MIPS MT</tt>, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors.
 
The early [[MIPS]] architectures were 32-bit implementations (generally 32-bit wide registers and data paths), while later versions were 64-bit implementations. Five backward-compatible revisions of the MIPS instruction set exist, named <tt>MIPS I</tt>, <tt>MIPS II</tt>, <tt>MIPS III</tt>, <tt>MIPS IV</tt>, and <tt>MIPS 32/64</tt>. The latest of these, <tt>MIPS 32/64</tt> Release 2, defines a control register set as well as the instruction set. Several "add-on" extensions are also available, including <tt>MIPS-3D</tt> which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, <tt>MDMX(MaDMaX)</tt> which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, <tt>MIPS16</tt> which adds compression to the instruction stream to make programs take up less room (allegedly a response to the ARM architecture encoding in the ARM architecture), and the recent addition of <tt>MIPS MT</tt>, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors.
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Because the designers created such a [[#Summary of R3000 instruction set|clean instruction set]], computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the [[MIPS]] CPU family greatly influenced later RISC architectures such as DEC Alpha.
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Because the designers created such a [[#Summary of R3000 instruction set|clean instruction set]], computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the [[MIPS]] CPU family greatly influenced later RISC architectures such as [[DEC Alpha]].
    
==History==
 
==History==
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== Applications ==
 
== Applications ==
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Among the manufacturers which made computer workstation systems using MIPS processors are Silicon Graphics|SGI, MIPS Computer Systems, Inc., Olivetti, Siemens Nixdorf Informationssysteme|Siemens-Nixdorf, Acer (company)|Acer, Digital Equipment Corporation, NEC Corporation|NEC, and DeskStation. Various operating systems have been ported to the architecture, such as SGI's IRIX, Microsoft's Windows NT (although support for MIPS ended with the release of Windows NT 4.0) and Windows CE, Linux, BSD, Unix|UNIX System V, SINIX, MIPS Computer Systems' own RISC/os, and others.
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Among the manufacturers which made computer workstation systems using MIPS processors are [[Silicon Graphics]]|SGI, MIPS Computer Systems, Inc., Olivetti, Siemens Nixdorf Informationssysteme|Siemens-Nixdorf, Acer (company)|Acer, Digital Equipment Corporation, NEC Corporation|NEC, and DeskStation. Various operating systems have been ported to the architecture, such as SGI's [[IRIX]], Microsoft's Windows NT (although support for MIPS ended with the release of [[Windows NT 4.0]]) and Windows CE, Linux, BSD, Unix|UNIX System V, SINIX, MIPS Computer Systems' own RISC/os, and others.
    
However, use of MIPS as the main processor of computer workstations has declined, and SGI has announced its plans to cease developing high-performance iterations of the MIPS architecture in favor of using Intel IA64-based processors (see "Other models and future plans" section below).
 
However, use of MIPS as the main processor of computer workstations has declined, and SGI has announced its plans to cease developing high-performance iterations of the MIPS architecture in favor of using Intel IA64-based processors (see "Other models and future plans" section below).
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In 1997, a version of R10000 fabricated in a 0.25&nbsp;µm process enabled the microprocessor to reach 250 MHz.
 
In 1997, a version of R10000 fabricated in a 0.25&nbsp;µm process enabled the microprocessor to reach 250 MHz.
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== Users ==
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=== Users ===
    
The R10000 users were:
 
The R10000 users were:
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* Tandem Computers, in their Himilaya fault-tolerant servers
 
* Tandem Computers, in their Himilaya fault-tolerant servers
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== Description ==
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=== Description ===
The R10000 is a four-way [[superscalar]] design that implements [[register renaming]] and executes instructions [[Out-of-order execution|out-of-order]]. Its design was a departure from previous MTI microprocessors such as the R4000, which was a much simpler Scalar processor [[Out-of-order execution#In-order processors|in-order]] design that relied largely on high clock rates for performance.
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The R10000 is a four-way superscalar design that implements register renaming and executes instructions out-of-order. Its design was a departure from previous MTI microprocessors such as the R4000, which was a much simpler Scalar processor in-order design that relied largely on high clock rates for performance.
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The R10000 fetches four instructions every cycle from its instruction [[CPU cache|cache]]. These instructions are decoded and then placed into the integer, floating-point or load/store instruction queues depending on the type of the instruction. The decode unit is assisted by the pre-decoded instructions from the instruction cache, which append five bits to every instruction to enable the unit to quickly identify which execution unit the instruction is executed in, and rearrange the format of the instruction to optimize the decode process.
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The R10000 fetches four instructions every cycle from its instruction cache. These instructions are decoded and then placed into the integer, floating-point or load/store instruction queues depending on the type of the instruction. The decode unit is assisted by the pre-decoded instructions from the instruction cache, which append five bits to every instruction to enable the unit to quickly identify which execution unit the instruction is executed in, and rearrange the format of the instruction to optimize the decode process.
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Each of the instruction queues can accept up to four instructions from the decoder, avoiding any bottlenecks. The instruction queues issue their instructions to their execution units dynamically depending on the availability of [[operand]]s and resources. Each of the queues except for the load/store queue can issue up to two instructions every cycle to its execution units. The load/store queue can only issue one instruction. The R10000 can thus issue up to five instructions every cycle.
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Each of the instruction queues can accept up to four instructions from the decoder, avoiding any bottlenecks. The instruction queues issue their instructions to their execution units dynamically depending on the availability of operands and resources. Each of the queues except for the load/store queue can issue up to two instructions every cycle to its execution units. The load/store queue can only issue one instruction. The R10000 can thus issue up to five instructions every cycle.
    
===Integer unit===
 
===Integer unit===
The integer unit consists of the integer [[register file]] and three [[Instruction pipeline|pipeline]]s, two integer, one load store. The integer register file was 64 bits wide and contained 64 entries, of which 32 were architectural registers and 32 were rename registers used to implement register renaming. The register file had seven read ports and three write ports. Both integer pipelines have an [[Adder (electronics)|adder]] and a logic unit. However, only the first pipeline has a [[barrel shifter]] and hardware for confirming the prediction of conditional branches. The second pipeline is used to access the multiplier and divider. Multiplies are pipelined, and have a six-cycle latency for 32-bit integers and ten for 64-bit integers. Division is not pipelined. The divider uses a [[Non-restoring division|non-restoring algorithm]] that produces one bit per cycle. Latencies for 32-bit and 64-bit divides are 35 and 67 cycles, respectively.
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The integer unit consists of the integer register file and three pipelines, two integer, one load store. The integer register file was 64 bits wide and contained 64 entries, of which 32 were architectural registers and 32 were rename registers used to implement register renaming. The register file had seven read ports and three write ports. Both integer pipelines have an adder and a logic unit. However, only the first pipeline has a barrel shifter and hardware for confirming the prediction of conditional branches. The second pipeline is used to access the multiplier and divider. Multiplies are pipelined, and have a six-cycle latency for 32-bit integers and ten for 64-bit integers. Division is not pipelined. The divider uses a non-restoring algorithm that produces one bit per cycle. Latencies for 32-bit and 64-bit divides are 35 and 67 cycles, respectively.
    
===Floating-point unit===
 
===Floating-point unit===
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The R10000 used the Avalanche bus, a 64-bit bus that operated at frequencies up to 100&nbsp;MHz. Avalanche is a multiplexed address and data bus, so at 100&nbsp;MHz it yielded a maximum theoretical bandwidth of 800&nbsp;MB/s, but its peak bandwidth was 640&nbsp;MB/s as it required some cycles to transmit addresses.
 
The R10000 used the Avalanche bus, a 64-bit bus that operated at frequencies up to 100&nbsp;MHz. Avalanche is a multiplexed address and data bus, so at 100&nbsp;MHz it yielded a maximum theoretical bandwidth of 800&nbsp;MB/s, but its peak bandwidth was 640&nbsp;MB/s as it required some cycles to transmit addresses.
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The system interface controller supported glue-less [[symmetrical multiprocessing]] (SMP) of up to four microprocessors. Systems using the R10000 with external logic could scale to hundreds of processors. An example of such a system is the [[Origin 2000]].
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The system interface controller supported glue-less symmetrical multiprocessing (SMP) of up to four microprocessors. Systems using the R10000 with external logic could scale to hundreds of processors. An example of such a system is the [[SGI Origin 2000]].
    
===Fabrication===
 
===Fabrication===
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The R12000 improved upon the R10000 microarchitecture by: inserting an extra pipeline stage to improve clock frequency by resolving a critical path; increasing the number of entries in the branch history table, improving prediction; modifying the the instruction queues so they take into account the age of a queued instruction, enabling older instructions were executed before newer ones if possible.
 
The R12000 improved upon the R10000 microarchitecture by: inserting an extra pipeline stage to improve clock frequency by resolving a critical path; increasing the number of entries in the branch history table, improving prediction; modifying the the instruction queues so they take into account the age of a queued instruction, enabling older instructions were executed before newer ones if possible.
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The R12000 was fabricated by NEC and Toshiba in a 0.25&nbsp;µm CMOS process with four levels of aluminum interconnect. The new use of a new process did not mean that the R12000 was a simple die shrink with a tweaked microarchitecture, the layout of the die was optimized to take advantage of the 0.25&nbsp;µm process.<ref>Gwennap, "MIPS R12000 to Hit 300 MHz".</ref><ref>Halfhill, "RISC Fights Bach with the Mips R12000".</ref> The NEC fabricated VR12000 contained 7.15 million transistors and measured 15.7 by 14.6&nbsp;mm (229.22&nbsp;mm<sup>2</sup>).
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The R12000 was fabricated by NEC and Toshiba in a 0.25&nbsp;µm CMOS process with four levels of aluminum interconnect. The new use of a new process did not mean that the R12000 was a simple die shrink with a tweaked microarchitecture, the layout of the die was optimized to take advantage of the 0.25&nbsp;µm process. The NEC fabricated VR12000 contained 7.15 million transistors and measured 15.7 by 14.6&nbsp;mm (229.22&nbsp;mm<sup>2</sup>).
    
=== R12000A ===
 
=== R12000A ===
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=== R14000 ===
 
=== R14000 ===
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The R14000 was a further development of the R12000 announced in July 2001. The R14000 operated at 500 MHz, enabled by the 0.13&nbsp;µm CMOS process with five levels of copper interconnect it was fabricated with. It featured improvements to the microarchitecture of the R12000 by supporting double data rate (DDR) SSRAMs for the secondary cache and a 200 MHz system bus.<ref name="TR-2002-07-02">"SGI to develop MIPS chips for Origin, Onyx"</ref>
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The R14000 was a further development of the R12000 announced in July 2001. The R14000 operated at 500 MHz, enabled by the 0.13&nbsp;µm CMOS process with five levels of copper interconnect it was fabricated with. It featured improvements to the microarchitecture of the R12000 by supporting double data rate (DDR) SSRAMs for the secondary cache and a 200 MHz system bus.
    
The R14000 is a typical representative of the modern RISC processors that are capable of out-of-order and speculative instruction execution. Like in the Compaq Alpha processor there are two independent floating-point units for addition and multiplication and, additionally, two units that perform floating division and square root operations (not shown in Figure 13). The latter, however, are not pipelined and with latencies of about 20--30 cycles are relatively slow. In all there are 5 pipelined functional units to be fed: an address calculation unit which is responsible for address calculations and loading/storing of data and instructions, two ALU units for general integer computation and the floating-point add and multiply pipes already mentioned.
 
The R14000 is a typical representative of the modern RISC processors that are capable of out-of-order and speculative instruction execution. Like in the Compaq Alpha processor there are two independent floating-point units for addition and multiplication and, additionally, two units that perform floating division and square root operations (not shown in Figure 13). The latter, however, are not pipelined and with latencies of about 20--30 cycles are relatively slow. In all there are 5 pipelined functional units to be fed: an address calculation unit which is responsible for address calculations and loading/storing of data and instructions, two ALU units for general integer computation and the floating-point add and multiply pipes already mentioned.
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=== R14000A ===
 
=== R14000A ===
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The R14000A was a further development of the R14000 announced in February 2002. It operated at 600 MHz, dissipated approximately 17&nbsp;W, and was fabricated by NEC Corporation in a 0.13&nbsp;µm CMOS process with seven levels of copper interconnect.<ref name="TR-2002-07-02"/>
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The R14000A was a further development of the R14000 announced in February 2002. It operated at 600 MHz, dissipated approximately 17&nbsp;W, and was fabricated by NEC Corporation in a 0.13&nbsp;µm CMOS process with seven levels of copper interconnect.
    
=== R16000 ===
 
=== R16000 ===
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The R16000, code-named "N0", was the last derivative of the R10000. It was developed by SGI and fabricated by NEC in their 0.11&nbsp;&micro;m process with eight levels of copper interconnect. The microprocessor was introduced on 9 January 2003, debuting at 700&nbsp;MHz for the [[SGI Fuel|Fuel]].<ref>Silicon Graphics, Inc., ''SGI Boosts Price/Performance on Silicon Graphics Fuel Visual Workstation Family up to 25%''.</ref> In April 2003, a 600&nbsp;MHz version was introduced for the [[SGI Origin 350|Origin 350]]. Improvements were 64&nbsp;KB instruction and data caches.
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The R16000, code-named "N0", was the last derivative of the R10000. It was developed by SGI and fabricated by NEC in their 0.11&nbsp;&micro;m process with eight levels of copper interconnect. The microprocessor was introduced on 9 January 2003, debuting at 700&nbsp;MHz for the [[SGI Fuel|Fuel]]. In April 2003, a 600&nbsp;MHz version was introduced for the [[SGI Origin 350|Origin 350]]. Improvements were 64&nbsp;KB instruction and data caches.
    
=== R16000A ===
 
=== R16000A ===
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The R16000 refers to R16000 microprocessors with clock rates higher than 700 MHz. The first R16000A was a 800 MHz version, introduced on 4 February 2004. Later, a 900 MHz version was introduced, and this version was for some time, the fastest publicly known R16000A&mdash;SGI later revealed there were 1.0&nbsp;GHz R16000s shipped to selected customers. R16000 users included HP and SGI. SGI used the microprocessor in their [[SGI Fuel|Fuel]] and [[SGI Tezro|Tezro]] workstations; and the [[Origin 3000]] servers and supercomputers. HP used the R16000A in their NonStop Himalaya S-Series fault-tolerant servers inherited from Compaq via Tandem.
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The R16000 refers to R16000 microprocessors with clock rates higher than 700 MHz. The first R16000A was a 800 MHz version, introduced on 4 February 2004. Later, a 900 MHz version was introduced, and this version was for some time, the fastest publicly known R16000A&mdash;SGI later revealed there were 1.0&nbsp;GHz R16000s shipped to selected customers. R16000 users included HP and SGI. SGI used the microprocessor in their [[SGI Fuel|Fuel]] and [[SGI Tezro|Tezro]] workstations; and the [[SGI Origin 3000]] servers and supercomputers. HP used the R16000A in their NonStop Himalaya S-Series fault-tolerant servers inherited from Compaq via Tandem.
    
=== R18000 ===
 
=== R18000 ===
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The R18000 improved the floating-point instruction queues and revised the floating-point unit to feature two multiply-add units, quadrupling the peak FLOPS count. Division and square-root were performed in separate non-pipelined units in parallel to the multiply-add units. The system interface and memory hierarchy was also significantly reworked. It would have a 52-bit virtual address and a 48-bit physical address. The bidirectional multiplexed address and data system bus of the R18000 would be replaced by two unidirectional DDR links, a 64-bit multiplexed address and write path and a 128-bit read path. Although they are unidirectional, each path could be shared by another R18000, although the two would be shared through multiplexing. The bus could also be configured in the SysAD or Avalanche configuration for backwards compatibility with R10000 systems.
 
The R18000 improved the floating-point instruction queues and revised the floating-point unit to feature two multiply-add units, quadrupling the peak FLOPS count. Division and square-root were performed in separate non-pipelined units in parallel to the multiply-add units. The system interface and memory hierarchy was also significantly reworked. It would have a 52-bit virtual address and a 48-bit physical address. The bidirectional multiplexed address and data system bus of the R18000 would be replaced by two unidirectional DDR links, a 64-bit multiplexed address and write path and a 128-bit read path. Although they are unidirectional, each path could be shared by another R18000, although the two would be shared through multiplexing. The bus could also be configured in the SysAD or Avalanche configuration for backwards compatibility with R10000 systems.
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The R18000 would have a 1&nbsp;MB four-way set-associative secondary cache would be included on-die; supplemented by an optional tertiary cache built from single data rate (SDR) or double data rate (DDR) SSRAM or DDR SDRAM with capacities of 2 to 64&nbsp;MB. The L3 cache had its cache tags, equivalent to 400&nbsp;KB, located on-die to reduce latency. The L3 cache is accessed via a 144-bit bus, of which 128 bits are for data and 8 bit for ECC. The L3 cache's clock rate was to have been programmable.
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The R18000 would have a 1&nbsp;MB four-way set-associative secondary cache would be included on-die; supplemented by an optional tertiary cache built from single data rate (SDR) or double data rate ([[DDR]]) SSRAM or DDR [[SDRAM]] with capacities of 2 to 64&nbsp;MB. The L3 cache had its cache tags, equivalent to 400&nbsp;KB, located on-die to reduce latency. The L3 cache is accessed via a 144-bit bus, of which 128 bits are for data and 8 bit for ECC. The L3 cache's clock rate was to have been programmable.
    
The R18000 was to be fabricated in NEC's UX5 process, a 0.13&nbsp;µm CMOS process with nine levels of copper interconnect. It would have used 1.2&nbsp;V power supply and dissipated less heat than contemporary server microprocessors in order to be densely packed into systems.
 
The R18000 was to be fabricated in NEC's UX5 process, a 0.13&nbsp;µm CMOS process with nine levels of copper interconnect. It would have used 1.2&nbsp;V power supply and dissipated less heat than contemporary server microprocessors in order to be densely packed into systems.
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[[Category:SGI]][[Category:Computing]]
 
[[Category:SGI]][[Category:Computing]]
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[[Category:Processors]]
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[[Category:MIPS]]

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