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110 bytes removed ,  23:31, 16 September 2018
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The R12000 improved upon the R10000 microarchitecture by: inserting an extra pipeline stage to improve clock frequency by resolving a critical path; increasing the number of entries in the branch history table, improving prediction; modifying the the instruction queues so they take into account the age of a queued instruction, enabling older instructions were executed before newer ones if possible.
 
The R12000 improved upon the R10000 microarchitecture by: inserting an extra pipeline stage to improve clock frequency by resolving a critical path; increasing the number of entries in the branch history table, improving prediction; modifying the the instruction queues so they take into account the age of a queued instruction, enabling older instructions were executed before newer ones if possible.
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The R12000 was fabricated by NEC and Toshiba in a 0.25&nbsp;µm CMOS process with four levels of aluminum interconnect. The new use of a new process did not mean that the R12000 was a simple die shrink with a tweaked microarchitecture, the layout of the die was optimized to take advantage of the 0.25&nbsp;µm process.<ref>Gwennap, "MIPS R12000 to Hit 300 MHz".</ref><ref>Halfhill, "RISC Fights Bach with the Mips R12000".</ref> The NEC fabricated VR12000 contained 7.15 million transistors and measured 15.7 by 14.6&nbsp;mm (229.22&nbsp;mm<sup>2</sup>).
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The R12000 was fabricated by NEC and Toshiba in a 0.25&nbsp;µm CMOS process with four levels of aluminum interconnect. The new use of a new process did not mean that the R12000 was a simple die shrink with a tweaked microarchitecture, the layout of the die was optimized to take advantage of the 0.25&nbsp;µm process. The NEC fabricated VR12000 contained 7.15 million transistors and measured 15.7 by 14.6&nbsp;mm (229.22&nbsp;mm<sup>2</sup>).
    
=== R12000A ===
 
=== R12000A ===

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