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=== R14000 ===
 
=== R14000 ===
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The R14000 was a further development of the R12000 announced in July 2001. The R14000 operated at 500 MHz, enabled by the 0.13&nbsp;µm CMOS process with five levels of copper interconnect it was fabricated with. It featured improvements to the microarchitecture of the R12000 by supporting double data rate (DDR) SSRAMs for the secondary cache and a 200 MHz system bus.<ref name="TR-2002-07-02">"SGI to develop MIPS chips for Origin, Onyx"</ref>
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The R14000 was a further development of the R12000 announced in July 2001. The R14000 operated at 500 MHz, enabled by the 0.13&nbsp;µm CMOS process with five levels of copper interconnect it was fabricated with. It featured improvements to the microarchitecture of the R12000 by supporting double data rate (DDR) SSRAMs for the secondary cache and a 200 MHz system bus.
    
The R14000 is a typical representative of the modern RISC processors that are capable of out-of-order and speculative instruction execution. Like in the Compaq Alpha processor there are two independent floating-point units for addition and multiplication and, additionally, two units that perform floating division and square root operations (not shown in Figure 13). The latter, however, are not pipelined and with latencies of about 20--30 cycles are relatively slow. In all there are 5 pipelined functional units to be fed: an address calculation unit which is responsible for address calculations and loading/storing of data and instructions, two ALU units for general integer computation and the floating-point add and multiply pipes already mentioned.
 
The R14000 is a typical representative of the modern RISC processors that are capable of out-of-order and speculative instruction execution. Like in the Compaq Alpha processor there are two independent floating-point units for addition and multiplication and, additionally, two units that perform floating division and square root operations (not shown in Figure 13). The latter, however, are not pipelined and with latencies of about 20--30 cycles are relatively slow. In all there are 5 pipelined functional units to be fed: an address calculation unit which is responsible for address calculations and loading/storing of data and instructions, two ALU units for general integer computation and the floating-point add and multiply pipes already mentioned.

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