Changes

The Grackle IC functions as the bridge between the PowerPC microprocessor bus and the I/O and graphics devices on the PCI bus. It provides buffering and address translation from one bus to the other.  

The Grackle IC functions as the bridge between the PowerPC microprocessor bus and the I/O and graphics devices on the [[PCI]] bus. It provides buffering and address translation from one bus to the other.  

The Grackle IC also provides the control and timing signals for ROM and RAM. The memory control logic supports byte, word, longword, and burst accesses to the system memory. If an access is not aligned to the appropriate address boundary, Grackle generates multiple data transfers on the bus.  

The Grackle IC also provides the control and timing signals for ROM and RAM. The memory control logic supports byte, word, longword, and burst accesses to the system memory. If an access is not aligned to the appropriate address boundary, Grackle generates multiple data transfers on the bus.  

The Grackle IC controls the system RAM and ROM and provides address multiplexing and refresh signals for the DRAM devices.

The Grackle IC controls the system RAM and ROM and provides address multiplexing and refresh signals for the DRAM devices.

The Grackle IC acts as a bridge between the processor bus and the PCI expansion bus, converting signals on one bus to the equivalent signals on the other bus. The PCI bridge functions are performed by two converters. One accepts requests from the processor bus and presents them to the PCI bus. The other converter accepts requests from the PCI bus and provides access to the RAM and ROM on the processor bus. The PCI bus bridge in the Grackle IC runs synchronously. The processor bus operates at a clock rate of 67 MHz, and the PCI bus operates at 30 or 33 MHz. The PCI bus bridge generates PCI parity as required by the PCI bus specification, but it does not check parity or respond to the parity error signal.  

The Grackle IC acts as a bridge between the processor bus and the [[PCI]] expansion bus, converting signals on one bus to the equivalent signals on the other bus. The PCI bridge functions are performed by two converters. One accepts requests from the processor bus and presents them to the PCI bus. The other converter accepts requests from the PCI bus and provides access to the RAM and ROM on the processor bus. The PCI bus bridge in the Grackle IC runs synchronously. The processor bus operates at a clock rate of 67 MHz, and the PCI bus operates at 30 or 33 MHz. The PCI bus bridge generates PCI parity as required by the PCI bus specification, but it does not check parity or respond to the parity error signal.  

=See Also=

=See Also=

[[Category:Apple]]

[[Category:Apple]]