Exponential X704

Features

The Exponential Technology X704 is a single-chip implementation of the 32-bit PowerPC architecture that conforms fully to the PowerPC Architecture Specification. The X704 processor features:

  • separate integer, load/store, branch, and floating-point units
  • up to three instructions issued each cycle
  • separate level 1 data and instruction caches
  • unified data and instruction level 2 cache
  • on-chip translation lookaside buffer (TLB)

Integer Unit

  • executes all arithmetic, logical, compare, rotate, and shift instructions except multiply and divide in a single cycle
  • executes multiply instructions in 3 to 6 cycles
  • bypasses results to following instructions with no delay

Load/Store Unit

  • supports issue of a load or store each cycle
  • handles all big-endian mode misaligned loads and stores in hardware
  • supports power-endian mode, including some misaligned accesses
  • forwards load data to the integer unit with no load-use penalty

Branch Unit

  • supports issue of a branch or condition register logical instruction each cycle
  • maintains 2-bit dynamic branch prediction in hardware
  • supports prediction through both PC-relative and indirect branches
  • no penalty for following correctly predicted branches
  • recovers quickly from mispredicted branches

Floating-Point Unit

  • complies with IEEE-754 single-precision and double-precision arithmetic standard
  • implements optional fsel and stfiwx instructions
  • supports denormalized numbers in hardware

Caches

  • 2-level cache hierarchy
  • 2KB direct-mapped instruction cache with 32-byte blocks
  • 2KB direct-mapped write through data cache with 32-byte blocks
  • 32KB 8-way set-associative unified level 2 cache with 32-byte blocks
  • supports write through and copy back protocols (level 2 cache)
  • supports all PowerPC cache operations
  • physically indexed and physically tagged caches
  • features 4-doubleword store queue between load/store unit and data/level 2 caches
  • features software disables
  • maps out damaged blocks and columns (level 2 cache)

Memory Management Unit

  • contains 128-entry, 4-way set-associative TLB with hardware-assisted software refill
  • contains four-entry, fully associative instruction TLB with hardware refill from main TLB
  • supports block address translation for four instruction blocks and four data blocks

MultiProcessing Support

  • supports MESI cache coherency protocol
  • supports lwarx and stwcx. memory synchronization instructions for atomic updates
  • broadcast synchronization of cache operations and serialization
  • broadcast TLB invalidates

Bus Interface

  • supports standard 64-bit data, 32-bit address 60x bus
  • supports data streaming with optional fast L2 mode
  • supports pipelined and split transactions
  • supports processor clock that is an integral multiple of bus clock

Test Interface

  • features JTAG TAP controller with boundary scan
  • proprietary scan access to all internal flip flops
  • supports scan access to all internal RAM structures
  • supports instruction-level access to all internal RAM structures
  • performs at-speed fault testing

Diagrams

Data Path