Difference between revisions of "O'Hare IC"
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Latest revision as of 16:25, 13 January 2022
The O’Hare IC is based on the Grand Central IC present in the Power Macintosh 7500 computer. It is an I/O controller and DMA engine for Power Macintosh computers using the PCI bus architecture. It provides power-management control functions for energy saving features included on Macintosh computers. The O’Hare IC is connected to the PCI bus and uses the 33 MHz PCI bus clock.
The O’Hare IC includes circuitry equivalent to the IDE, SCC, SCSI, sound, SWIM3, and VIA controller ICs. The functional blocks in the O’Hare IC include the following:
- support for descriptor-based DMA for I/O devices
- systemwide interrupt handling
- a SWIM3 floppy drive controller
- SCSI controller (MESH (Macintosh enhanced SCSI hardware) based)
- SCC serial I/O controller
- IDE hard disk interface controller
- sound control logic and buffers
The O’Hare IC provides bus interfaces for the following I/O devices:
- Cuda ADB controller IC (VIA1 and VIA2 registers)
- AWACS sound input and output IC
- 8 KB nonvolatile RAM control
- PWM outputs for brightness and contrast control
The SCSI controller in the O’Hare IC is a MESH controller. DMA channels in the O’Hare IC are used to support data transfers. The clock signal to the SCSI controller is 45 MHz.
The O’Hare IC also contains the sound control logic and the sound input and output buffers. There are two DMA data buffers—one for sound input and one for sound output—so the computer can record sound input and process sound output simultaneously. The data buffer contains interleaved right and left channel data for support of stereo sound.
The SCC circuitry in the O’Hare IC is an 8-bit device. The PCLK signal to the SCC is an 16 MHz clock. The SCC circuitry supports GeoPort and LocalTalk protocols.