https://wiki.preterhuman.net/index.php?title=R6000&feed=atom&action=history
R6000 - Revision history
2024-03-29T11:29:25Z
Revision history for this page on the wiki
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https://wiki.preterhuman.net/index.php?title=R6000&diff=12513&oldid=prev
Netfreak at 05:05, 26 May 2020
2020-05-26T05:05:18Z
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Netfreak
https://wiki.preterhuman.net/index.php?title=R6000&diff=9867&oldid=prev
Netfreak at 03:18, 21 July 2019
2019-07-21T03:18:47Z
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<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The '''R6000''' is a microprocessor chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS II]] [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The '''R6000''' is a microprocessor chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS II]] [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.</div></td></tr>
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Netfreak
https://wiki.preterhuman.net/index.php?title=R6000&diff=8757&oldid=prev
Netfreak at 08:01, 16 July 2019
2019-07-16T08:01:39Z
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Netfreak
https://wiki.preterhuman.net/index.php?title=R6000&diff=4145&oldid=prev
Netfreak at 18:06, 27 September 2018
2018-09-27T18:06:40Z
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<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></html></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The '''R6000''' is a microprocessor chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS II]] [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.</div></td><td class='diff-marker'> </td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The '''R6000''' is a microprocessor chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS II]] [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.</div></td></tr>
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Netfreak
https://wiki.preterhuman.net/index.php?title=R6000&diff=2941&oldid=prev
Netfreak: Created page with "The '''R6000''' is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS II [instruction set architecture (ISA). The chip set consiste..."
2018-09-16T08:21:15Z
<p>Created page with "The '''R6000''' is a microprocessor chip set developed by <a href="/MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a> that implemented the <a href="/index.php?title=MIPS_II&action=edit&redlink=1" class="new" title="MIPS II (page does not exist)">MIPS II</a> [instruction set architecture (ISA). The chip set consiste..."</p>
<p><b>New page</b></p><div>The '''R6000''' is a microprocessor chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS II]] [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.<br />
<br />
The R6000 was implemented with emitter-coupled logic (ECL). In the mid- to late 1980s, the trend was to implement high-end microprocessors with high-speed logic such as ECL. As MIPS was a fabless company, the R6000 chip set was fabricated by Bipolar Integrated Technology.<br />
<br />
The R6000 had few users. Control Data Systems (CDS) used an 80 MHz version in their high-end 4680-300 Series InforServer server. MIPS used the R6000 in their RC6260 and RC6280 servers.<br />
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==References==<br />
* "MIPS Chip Set Implements Full ECL CPU". (December 1989). ''Microprocessor Report''. pp. 1, 14&ndash;19.<br />
* Horowitz, M. et al. (1990). [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=110133 "A 3.5ns, 1 Watt, ECL register file"]. ''ISSCC Digest of Technical Papers'', pp. 68&ndash;59, 267.<br />
* Roberts, D.; Layman, T.; Taylor, G. (1990). [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=63680 "An ECL RISC microprocessor designed for two level cache"]. ''Compcon Spring '90 Digest of Technical Papers'', pp. 228&ndash;231.<br />
<!--* Taylor, G. et al. (1990). "An 85 MHz ECL RISC processor with on-chip address translation and two-level cache control". ''ISSCC Digest of Technical Papers'', pp. 40&ndash;41..--><br />
* Thorson, M. (January 1990). "ECL Bus Controller Hits 266 Mbytes/s". ''Microprocessor Report''. pp. 12&ndash;13.<br />
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[[Category:SGI]]</div>
Netfreak