Please consider a donation to the Higher Intellect project. See https://preterhuman.net/donate.php or the Donate to Higher Intellect page for more info.

Difference between revisions of "XIO"

From Higher Intellect Vintage Wiki
Jump to navigation Jump to search
(Created page with "== What is XIO? == XIO is a high-speed communications channel, used for most newer SGI systems (IP27, IP30, IP35 - note the O2 is NOT a XIO sys...")
 
 
(5 intermediate revisions by the same user not shown)
Line 1: Line 1:
 +
<html>
 +
<script async src="//pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script>
 +
<!-- misc-responsive -->
 +
<ins class="adsbygoogle"
 +
    style="display:block"
 +
    data-ad-client="ca-pub-8542359430745061"
 +
    data-ad-slot="5971110325"
 +
    data-ad-format="auto"
 +
    data-full-width-responsive="true"></ins>
 +
<script>
 +
(adsbygoogle = window.adsbygoogle || []).push({});
 +
</script>
 +
</html>
 +
 
== What is XIO? ==
 
== What is XIO? ==
  
XIO is a high-speed communications channel, used for most newer SGI systems ([[IP27]], [[IP30]], [[Origin300|IP35]] - note the [[IP32|O2]] is NOT a XIO system). It's typically used in a switched star topology, the switch being called [[XBow]].
+
XIO is a high-speed communications channel, used for most newer SGI systems ([[IP27]], [[IP30]], [[SGI Origin 300|IP35]] - note the [[SGI O2]] is NOT a XIO system). It's typically used in a switched star topology, the switch being called [[XBow]].
  
 
XIO devices are called [[widget|widgets]].
 
XIO devices are called [[widget|widgets]].
Line 8: Line 22:
 
'''XIO''' is a packet-based, high-performance computer bus employed by [[SGI Octane]], [[SGI Origin|Origin]], [[SGI Altix|Altix]], [[SGI Fuel|Fuel]] and [[SGI Tezro|Tezro]] machines. It forms a bus between high-performance system devices and the memory controller. XIO devices are called "widgets".
 
'''XIO''' is a packet-based, high-performance computer bus employed by [[SGI Octane]], [[SGI Origin|Origin]], [[SGI Altix|Altix]], [[SGI Fuel|Fuel]] and [[SGI Tezro|Tezro]] machines. It forms a bus between high-performance system devices and the memory controller. XIO devices are called "widgets".
  
XIO is usually used in a star topology -- a router called '''Xbow''' (cross-bow) connects up to eight fully-symmetrical devices in a system (typically, one of them is the memory controller / CPU bridge, called HEART in [[Octane]] or HUB in [[Origin]]).
+
XIO is usually used in a star topology -- a router called '''Xbow''' (cross-bow) connects up to eight fully-symmetrical devices in a system (typically, one of them is the memory controller / CPU bridge, called HEART in [[SGI Octane]] or HUB in [[Origin]]).
  
 
Other devices known to have XIO interfaces are:
 
Other devices known to have XIO interfaces are:
* BRIDGE: XIO to PCI-64 bridge ([[Octane]], [[Origin]])
+
* BRIDGE: XIO to PCI-64 bridge ([[SGI Octane]], [[Origin]])
 
* XBRIDGE: XIO to PCI-X bridge ([[Altix]])
 
* XBRIDGE: XIO to PCI-X bridge ([[Altix]])
* HQ4: command processor of ImpactSR cards ([[Octane]])
+
* HQ4: command processor of ImpactSR cards ([[SGI Octane]])
* KTOWN: frontend for InfiniteReality2 cards ([[Onyx]], [[Origin]] variation)
+
* KTOWN: frontend for InfiniteReality2 cards ([[SGI Onyx]], [[Origin]] variation)
 
* XC: Crosstown converter
 
* XC: Crosstown converter
  
  
XIO employs two source-synchronous channels (one in each direction), each 8 or 16 bits wide. They are clocked at 400 MHz to achieve peak rates of 800 MB/s. Each of the devices can utilize the full bandwidth, as the XBow router prevents collisions by being able to route between any two points.
+
XIO employs two source-synchronous channels (one in each direction), each 8 or 16 bits wide. They are clocked at 400 MHz to achieve peak rates of 800 MB/s. Each of the devices can utilize the full bandwidth, as the [[XBow]] router prevents collisions by being able to route between any two points.
  
 
Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16).
 
Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16).
Line 26: Line 40:
  
 
XIO boards use very fragile compression connectors, which should be handled with extreme care.
 
XIO boards use very fragile compression connectors, which should be handled with extreme care.
 
 
  
 
== Physical layer ==
 
== Physical layer ==
Line 35: Line 47:
 
== Link layer ==
 
== Link layer ==
  
XIO contains a link-layer protocol (LLP) shared with [[CrayLink]]. Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits ([http://en.wikipedia.org/wiki/Cyclic_redundancy_check CRC-16]).
+
XIO contains a link-layer protocol (LLP) shared with CrayLink. Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits ([http://en.wikipedia.org/wiki/Cyclic_redundancy_check CRC-16]).
  
 
The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.
 
The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.
Line 43: Line 55:
 
XIO supports basic read/write memory transactions. IRQs are sent through XIO by instructing a device to write a defined value to some register in another XIO widget. This write actually triggers the IRQ handling process in the interrupt controller. For instance, the [[SGI_Octane#HEART|HEART]] chip has such register at 0x80 in XIO widget space.
 
XIO supports basic read/write memory transactions. IRQs are sent through XIO by instructing a device to write a defined value to some register in another XIO widget. This write actually triggers the IRQ handling process in the interrupt controller. For instance, the [[SGI_Octane#HEART|HEART]] chip has such register at 0x80 in XIO widget space.
  
XIO addresses differ from physical processor addresses. They are two-part (widget-offset) and each XIO device is free to implement the translation from its unified memory space to the XIO address. [[BRIDGE]] and [[SGI_Octane#HEART|HEART]] are examples of two different approaches.
+
XIO addresses differ from physical processor addresses. They are two-part (widget-offset) and each XIO device is free to implement the translation from its unified memory space to the XIO address. BRIDGE and [[SGI_Octane#HEART|HEART]] are examples of two different approaches.
  
 
== Device identification ==
 
== Device identification ==

Latest revision as of 23:03, 2 October 2018

What is XIO?

XIO is a high-speed communications channel, used for most newer SGI systems (IP27, IP30, IP35 - note the SGI O2 is NOT a XIO system). It's typically used in a switched star topology, the switch being called XBow.

XIO devices are called widgets.


XIO is a packet-based, high-performance computer bus employed by SGI Octane, Origin, Altix, Fuel and Tezro machines. It forms a bus between high-performance system devices and the memory controller. XIO devices are called "widgets".

XIO is usually used in a star topology -- a router called Xbow (cross-bow) connects up to eight fully-symmetrical devices in a system (typically, one of them is the memory controller / CPU bridge, called HEART in SGI Octane or HUB in Origin).

Other devices known to have XIO interfaces are:

  • BRIDGE: XIO to PCI-64 bridge (SGI Octane, Origin)
  • XBRIDGE: XIO to PCI-X bridge (Altix)
  • HQ4: command processor of ImpactSR cards (SGI Octane)
  • KTOWN: frontend for InfiniteReality2 cards (SGI Onyx, Origin variation)
  • XC: Crosstown converter


XIO employs two source-synchronous channels (one in each direction), each 8 or 16 bits wide. They are clocked at 400 MHz to achieve peak rates of 800 MB/s. Each of the devices can utilize the full bandwidth, as the XBow router prevents collisions by being able to route between any two points.

Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16). The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.

XIO is usually used on a single-ended, source-synchronous physical layer (STL levels - SGI Transistor Logic). There is also a version called Crosstown, which uses normal cabling and differential Positive Referenced Emitter Coupled Logic (PECL) transmission.

XIO boards use very fragile compression connectors, which should be handled with extreme care.

Physical layer

XIO is usually used on a single-ended, source-synchronous physical layer (STL levels - SGI Transistor Logic). It's either an 8- or 16-bit channel, running at 400 MHz (using the dreaded compression connectors). There is also a version, called Crosstown, that uses normal cabling and differential PECL transmission.

Link layer

XIO contains a link-layer protocol (LLP) shared with CrayLink. Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16).

The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.

Transactions

XIO supports basic read/write memory transactions. IRQs are sent through XIO by instructing a device to write a defined value to some register in another XIO widget. This write actually triggers the IRQ handling process in the interrupt controller. For instance, the HEART chip has such register at 0x80 in XIO widget space.

XIO addresses differ from physical processor addresses. They are two-part (widget-offset) and each XIO device is free to implement the translation from its unified memory space to the XIO address. BRIDGE and HEART are examples of two different approaches.

Device identification

There is no distinction between memory and configuration space in XIO. Instead, each XIO device has a predefined header that consists of a widget ID and several configuration registers.